SEMICONDUCTOR INTEGRATED CIRCUIT, AND CIRCUIT LAYOUT APPARATUS, METHOD, AND PROGRAM

摘要

PROBLEM TO BE SOLVED: To prevent hold time error while suppressing increase in wiring length without inserting a buffer for adjusting delay. SOLUTION: Assuming that a hold time error does not occurs between flipflops FF11 and FF13 but occurs between flipflops FF12 and FF13, the flipflops FF11 and FF13 reconnect scan paths P41-P44 in the order for shortening the wiring, and the flipflops FF12 and FF13 reconnect the scan paths P41-P44 in the order of late arriving time of clock. COPYRIGHT: (C)2007,JPO&INPIT