发明名称 Method and apparatus for reducing jitter
摘要 A jitter reducing method in a receiver of a selective combining system includes determining a slowest cell corresponding to the receiver in the selective combining system, treating a plurality of missing packets as being received when a data stream transmitted by the slowest cell is detected to comprise the plurality of missing packets and a sequence number of a first packet in the plurality of missing packets is a sequence number of a next packet that is expected to be received in sequence, and delivering a received packet following the plurality of missing packets in sequence to an upper layer.
申请公布号 EP1718016(A2) 申请公布日期 2006.11.02
申请号 EP20060008828 申请日期 2006.04.27
申请人 ASUSTEK COMPUTER INC. 发明人 JIANG, SAM SHIAW-SHIANG
分类号 H04L12/64;H04W74/06;H04W84/18 主分类号 H04L12/64
代理机构 代理人
主权项
地址