| 摘要 |
<p>A redundancy judge circuit 3 includes a redundancy judge circuit address +1 controller 30, an even-numbered redundant address judge section 31, an odd-numbered redundancy judge section 32, a redundant address ROM 33, a redundant IOROM 34, and a select section 35. A redundancy judge circuit 3 corresponding to a 2-bit prefetch operation shown in Fig. 2 is incorporated into circuits (a memory cell circuit 2, a read circuit 4, a the address generator circuit 5) corresponding to 2-bit prefetch operation shown in Fig. 1. With this structure, the redundancy remedy can be conducted even in the burst operation due to the 2-bit prefetch, and a fear that a read operation speed becomes low can be prevented. Because it is possible to reduce the wiring length of a decode signal bus in a column direction to substantially half, and to reduce a decode signal bus region to substantially half, it is possible to prevent a fear that the wiring density in the wiring region of the decode signal bus becomes high and to increase the read speed.</p> |
