发明名称 TCP/IP TRANSMISSION PROCESSING CIRCUIT AND SEMICONDUCTOR INTEGRATED CIRCUIT PROVIDED WITH THE SAME
摘要 <p><P>PROBLEM TO BE SOLVED: To provide a TCP/IP transmission processing circuit or the like capable of calculating a check sum of an IP header and a check sum of the TCP or the UDP. <P>SOLUTION: The TCP/IP transmission processing circuit 5 includes: a buffer memory 24; a check sum calculation processing section 25 for calculating the check sum of the IP header and the check sum of the TCP or the UDP; a DMA processing section 21 for applying DMA transfer to a frame generated by a higher-order layer; and a check sum control section 22 that receives the frame, writes the frame to the buffer memory 24, allows the check sum calculation processing section 25 to calculate the check sum of the IP header, thereafter allows the check sum calculation processing section 25 to calculate the check sum of the TCP or the UPD, inserts the check sum of the IP header and the check sum of the TCP or the UDP into the frame stored in the buffer memory 24, and transfers the resulting frame to a lower-order layer. <P>COPYRIGHT: (C)2007,JPO&INPIT</p>
申请公布号 JP2006303765(A) 申请公布日期 2006.11.02
申请号 JP20050120776 申请日期 2005.04.19
申请人 SEIKO EPSON CORP 发明人 HIGUCHI CHISATO
分类号 H04L12/951 主分类号 H04L12/951
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