发明名称 Technique for compensating for substrate shrinkage during manufacture of an electronic assembly
摘要 Substrate shrinkage that occurs during manufacture of an electronic assembly (100A) is compensated for by the incorporation of a horizontal line (102,104), having a plurality of vertical graduations, across a horizontal portion of a substrate (100) and a vertical line (106,108), having a plurality of horizontal graduations, across a vertical portion of the substrate (100). The substrate (100) is then cured and an amount of substrate shrinkage is determined, based upon a location change in the graduations of the horizontal and vertical lines (102,104,106,108). In this manner, solder can be properly provided on solder pads of the substrate (100) responsive to the amount of substrate shrinkage. As such, electronic components (110,112,114,116) can be properly mounted to the solder pads of the substrate (100).
申请公布号 EP1718138(A2) 申请公布日期 2006.11.02
申请号 EP20060075721 申请日期 2006.03.29
申请人 DELPHI TECHNOLOGIES, INC. 发明人 FAIRCHILD, M. RAY;BADGET, JEROME L.
分类号 H05K3/00 主分类号 H05K3/00
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