METHOD FOR ESTIMATING CLOCK JITTER FOR STATIC TIMING MEASUREMENTS OF MODELED CIRCUITS

摘要

A method in accordance with the invention for modeling period jitter for testing a modeled logic circuit. Clock signals can be derived from a phase lock loop having a voltage controlled oscillator for use to evaluate timing problems within a modeled circuit. An estimation of period jitter for the modeled clock signals can be made by considering the number of periods of the voltage controlled oscillator signal which generates the clock signal occurring within a test interval. By using the relationship as an index to a table, a value of period jitter may be obtained from a table which increases longer the timing interval being considered. Instructions for carrying out the steps of correcting intervals between clock signals used in static timing tests may be stored on a computer readable medium along with a table containing the amount of period jitter as a function of the number of VCO periods occurring within a testing period. The improved accuracy in period jitter estimation improves the reliability of static testing of modeled circuits.