| 摘要 |
A semiconductor memory device is provided to reduce unnecessary current consumption in an idle state and a bank active state, by driving a flip flop only during a write operation and a read operation requiring the generation of an actual internal column-address. A first driving clock supply unit(300) supplies a first driving clock during a read or write operation of a corresponding bank. A second driving clock supply unit(400) supplies a second driving clock during the write operation of the corresponding bank. A read address generation unit(100) outputs an internal address received in response to a CAS signal as an AL address corresponding to additive latency, outputs a read-address synchronized with a read CAS signal, and is driven in synchronization with the first driving clock. A write address generation unit(200) is synchronized with the second driving clock, and outputs the AL address as a write-address by delaying the AL address by the time period corresponding to CAS latency. An address output unit(500) latches the read-address or the write-address and then outputs the latched read-address or the latched-write address as an internal column-address.
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