发明名称 AUTOMATIC FLOOR PLANNING TECHNIQUE FOR SEMICONDUCTOR INTEGRATED CIRCUIT
摘要 PROBLEM TO BE SOLVED: To determine the placement position, shape and area of blocks more easily for chip level optimization in floor plan design by a virtual flat placement technique having a black box block. SOLUTION: A preset black box block is provided with a flexible shape and area, so that the shape and area of the black box block can reflect effects of chip level routing congestion and the like, and can further reflect effects of chip level routing congestion and the like because the shape and area of the preset black box block lightly affects blocks other than the black box. Block shapes can thus be determined more easily for chip level optimization to shorten the design period of a semiconductor integrated circuit. COPYRIGHT: (C)2007,JPO&INPIT
申请公布号 JP2006301961(A) 申请公布日期 2006.11.02
申请号 JP20050122740 申请日期 2005.04.20
申请人 MATSUSHITA ELECTRIC IND CO LTD 发明人 FUKAZAWA HIROKIMI
分类号 G06F17/50;H01L21/82 主分类号 G06F17/50
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