发明名称 FILTER ARITHMETIC DEVICE
摘要 <p>A filter operation apparatus according to the present invention involves a vertical and horizontal half-pixel motion compensation and vertical and horizontal intra-loop filtering means 100 comprising a first pixel delay means 200, a second pixel delay means 201, a multiplication means 202, a left shift means 203, a first selection means 204, an addition means 205, a second selection means 206, a selection control signal generation means 207, a third pixel delay means 208, a right shift means 209, and a shift amount control means 210. The so-constructed operation apparatus can share an operation unit in a horizontal processing apparatus and a vertical processing apparatus in the processing of half-pixel motion compensation and intra-loop filtering for input pixel data, thereby reducing the scale of hardware. &lt;IMAGE&gt;</p>
申请公布号 EP1056295(B1) 申请公布日期 2006.11.02
申请号 EP19990959748 申请日期 1999.12.10
申请人 MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD. 发明人 NAKAMURA, TSUYOSHI;OOHASHI, MASAHIRO;KUROMARU, SHUNICHI
分类号 G06T5/20;H04N19/42;H04N19/50;H04N19/523;H04N19/80;H04N19/82 主分类号 G06T5/20
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