发明名称 MULTIPROCESSOR SYSTEM
摘要 PROBLEM TO BE SOLVED: To provide a multiprocessor system having a plurality of processors which can be easily constructed. SOLUTION: A control circuit 7 has: a first operation mode allowing a JTAG debugger to debug the processors 2, 3 as is conventionally generally known; and a second operation mode for controlling a debug function of the processor 3 by being controlled by the processor 2. In normal use, the control circuit 7 is set to the second operation mode. That is, the processor 2 controls a debug function part 36 of the control circuit 7, thereby selectors 42, 43, 44, 45 select a TDI signal, a TRST signal, a TCK signal, and a TMS signal outputted by the debug function part 36, a selector 46 selects a TDO signal outputted by the processor 2, and the debug function part 36 inputs the TDO signal outputted by the processor 3. COPYRIGHT: (C)2007,JPO&INPIT
申请公布号 JP2006302162(A) 申请公布日期 2006.11.02
申请号 JP20050125936 申请日期 2005.04.25
申请人 FUJITSU LTD 发明人 YODA RYUICHI
分类号 G06F11/28 主分类号 G06F11/28
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