| 摘要 |
PROBLEM TO BE SOLVED: To provide a memory device allowing a CPU having a bus of N (wherein N is an integer of 2 or above)×8 bits to acquire or write N-byte data by one access. SOLUTION: This memory device is provided with: four memories 50-53 each having an address space (0x000-0x3FF) of the same scale having a common address with one word as one byte; an address decoder 30 allowing simultaneous access in arbitrary byte alignment to the four memories 50-53; and a data rearrangement circuit 70 rearranging data compliant with a big-endian CPU. COPYRIGHT: (C)2007,JPO&INPIT
|
