| 摘要 |
A power throttling method and system for a memory controller. In one embodiment, at least a first and a second throttle value are provided in the memory controller, the first and second throttle values for controlling memory operation cycles issued by the memory controller to one or more memory devices. Responsive to a throttle control signal, the memory controller selects a lower value of the first and second throttle values, whereby the memory operation cycles are issued to the memory devices at a reduced rate.
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