| 摘要 |
<p><P>PROBLEM TO BE SOLVED: To reduce the burden on an ECU (Electronic Control Unit) by averaging DF (Duty Factor) signals through an inexpensive and convenient arrangement. <P>SOLUTION: A DF signal averaging circuit 12 comprises a counter 14 performing count operation by receiving a clock signal from a clock signal generator 13, an OR circuit 15 receiving the clock signal and the positive pole side potential signal of a transistor 7 and causing the counter 14 to perform count-up operation only when the transistor 7 is turned on, a storage circuit 16 for operating an averaged DF signal based on an output value read out from the counter 14 at a predetermined timing, and a preset control circuit 17 for operating a preset value based on the averaged DF signal from the storage circuit 16 at a predetermined timing and presetting the counter 14 with that preset value wherein the output from the storage circuit 16 is delivered, as an averaged DF signal, to an ECU or an external controller 19 through a communication interface IF 18. <P>COPYRIGHT: (C)2007,JPO&INPIT</p> |
