发明名称 Elektrische Schaltanordnung mit mehr als zwei stabilen Betriebszustaenden
摘要 822,340. Electronic counting apparatus. INTERNATIONAL BUSINESS MACHINES CORPORATION. Jan. 2, 1956 [Jan. 3, 1955], No. 48/56. Class 106 (1). [Also in Group XL (c)] In a circuit employing an amplifying device with feed-back, including a transistor or discharge tube, between the output and input, an impedance is connected as a load which varies between high and low values with varying applied potentials to give a number of stable states. The junction transistors 1, 2, Fig. 1, are reciprocally coupled and assumes a stable state if the network 4 is of low impedance and an unstable state if the network impedance is high. The main supply 14 is of much greater potential than those of supplies 12, 17, 20 and 22 which decrease negatively in that order. The collector potential of transistor 1 takes its most negative value when diode 11 conducts, Fig. 3, and the section A of load line 44 on the Ic/Vc characteristic is traced out as the potential is raised. When diode 11 is biased off the impedance presented to the collector rises to the value of resistor 13, section B, continuing at this value until diode 15 conducts when the impedance falls to a low value, section C. A further rise in potential biases off diode 16 and the impedance becomes that of resistors 13 and 23 in parallel, section D. This process is repeated over sections E, F until diode 21 conducts to limit further rise, section G. The circuit operates at the middle of the stable sections A, C, E, and G and is moved from one to the other by input pulses applied to an auxiliary transistor 3. The resistors 26, 27 and 28 are so chosen that the junction 29 assumes a potential one step more positive than that of the collector 1c and junction 31 is slightly positive with respect to junction 29, so that transistor 3 is normally cut off. Assuming the potential of the collector 1c is Ea then the potential of junction 29 is Ec so that a negative going pulse applied to the base of transistor 3 causes the collector to approach closely to the potential of the emitter so that the base of transistor 2 assumes a potential of Ec. Since the base potential is raised the current flow in resistor 5 decreases with a corresponding increase in the emitter current of transistor 1 since the current in resistor 6 is maintained constant. Each incoming pulse steps the circuit on until the emitter of transistor 2 has risen sufficiently to overcome the bias on diode 36 and an output pulse 41 is generated. By employing a series of diodes 67, 68, Fig. 4, a decimal counter may be constructed with the diodes 68 of the network energized from a single supply 53. The circuit is set to zero by operating switch 81 which puts a negative potential on the emitter lead of transistor 1 causing it to cut off and the collector to be caught by clamping diode 65. Negative-going pulses are applied over terminal 51 to emitterfollower 46 from which they are fed at low impedance to the auxiliary transistor 3 which steps on the circuit in the manner described with reference to Fig. 1. Upon the receipt of the ninth pulse diode 71 conducts and the emitter potential of transistor 2 rises sufficiently to feed a pulse out over diode 36. The tenth pulse is effective over diode 201 and capacitor 203 to cut off the transistor 1 and restore the circuit to its original state. The circuit may be reset by a simple battery and switch, Fig. 5 (not shown), and the auxiliary transistor 3 may be replaced by a battery 89 and capacitor 85, 86, Fig. 6, and switch 88 pulses being fed over diode 84 to the line 73, Fig. 4. In a further modification, Fig. 7, positive-going pulses are fed in over diode 209 to the emitter of transistor 1, a further resistor 206 and capacitor 207 being added, the time constants of the circuit 210, 212 and 206, 207 being chosen of the same value. When it is desired to count down, the circuits of Figs. 1 and 4 may be modified according to Fig. 8, positivegoing pulses being applied over terminal 228 to emitter follower 224 which cause transistor 214 to conduct lowering the potential of collector 1c by one step. When the lowest potential is reached diode 231 conducts to reset the circuit. The polarity of the diode 36 and battery 38 are reversed, Fig. 9 (not shown). In a further modification, Fig. 11, employing transistors 90, 91, the circuit is stable when the impedance of network 92 is high and unstable when it is low. A circuit employing two PNP transistors may be employed connected to terminal 94, Fig. 12 (not shown). The circuit of Fig. 1 may be operated from a single common battery, Fig. 14 (not shown). A count of ten may be obtained by applying input pulses to a normal binary stage feeding a scale-of-five circuit. A network 181, Fig. 17, may be employed between transistors 1, 2 comprising Zener diodes 182, 183, 184 and 185, these diodes having an impedance which is low in the forward and Zener region. At the lowest collector potential all the diodes conduct in the Zener state and presents a low impedance. As the potential rises, each diode in turn passes through its high resistance region and gives a high impedance to the network, Fig. 18 (not shown). As an alternative to the use of two junction transistors a single point contact transistor may be used, Fig. 19 (not shown). Thermionic discharge tubes may be used, Fig. 15, the output from grounded grid pentode 146 being applied to the network 148 and thence to the cathode follower 147, the cathode of tube 146 being returned to a tapping on the cathode load. Normally the anode potential of pentode 146 is clamped by diode 175 conducting to the potential of battery 176. The circuit remains stable whilst diode 175 conducts, section R, Fig. 16, but when the potential of the anode falls sufficiently for diode 175 to cut off, the load becomes resistor 177 and the circuit is unstable, section 8. At some lower potential diode 169 conducts to give a stable section T until diode 170 ceases to conduct and the load rises to that of resistors 172 and 177 in parallel to give the unstable section U. The process is continued over the remaining sections.
申请公布号 DE1054117(B) 申请公布日期 1959.04.02
申请号 DE1956I011141 申请日期 1956.01.03
申请人 IBM DEUTSCHLAND INTERNATIONALE BUERO-MASCHINEN GESELLSCHAFT M.B.H. 发明人 HENLE ROBERT ATHANASIUS;LOGUE JOSEPH CARL
分类号 H03K3/2893;H03K23/00 主分类号 H03K3/2893
代理机构 代理人
主权项
地址