ADDRESS DECODING CIRCUIT AND ADDRESS DECODING METHOD

摘要

An address decoder circuit and method are provided to reduce fabrication cost of a semiconductor device including a memory bank, by reducing the layout area of the memory bank. An N number of Y decoding driver columns are arranged along an Y address axis on the center region of the regions formed by dividing an X address axis by N on the layout of a memory bank, and output a switching signal of an Y enable switch of a memory cell. An Y address decoder selects an Y decoding driver column to be enabled among the Y decoding driver columns with a partial address of input Y addresses, and controls the selected Y decoding driver column to enable a corresponding Y address line with the other partial address of the input Y addresses.