BUS SYSTEM AND BUS DATA PROCESSING METHOD FOR SYSTEM ON CHIP

摘要

An SoC(System on Chip) bus system and a bus data processing method thereof are provided to minimize a system design area and data transfer latency by forming FIFO(First Input First Output) memories present in each IP(Intellectual Property) into one FIFO block when an SoC is designed. A microcontroller requests a data operation process by allocating one target IP among the IPs(40) performing a different function. A relay previously stores data received through a bus to an idle memory according to the data operation process of a master IP(20) and transfers the data stored in the memory to the target IP in case that a high-state read signal is received from the target IP. The relay includes more than one memory(32), a bus interface(31) transceiving the data by interfacing with the bus, an IP interface(33) transceiving the data by interfacing with more than one IP, and a controller(34).