发明名称 Efficient implementation of a bypassable flip-flop with a clock enable
摘要 A flip-flop circuit includes a flip-flop, a first pass gate, a second pass gate, and a third pass gate. The first pass gate has an input to receive an input signal, an output coupled to the flip-flop's data input, and a control terminal to receive a first control signal. The second pass gate has an input coupled to the flip-flop's data input, an output coupled to the circuit's output, and a control terminal to receive a second control signal. The third pass gate has an input coupled to the flip-flop's data output, an output coupled to the circuit's output, and a control terminal to receive a third control signal. The first, second, and third control signals may be generated in response to various logical combinations of a bypass signal and a clock enable signal.
申请公布号 US7129762(B1) 申请公布日期 2006.10.31
申请号 US20050059967 申请日期 2005.02.17
申请人 XILINX, INC. 发明人 VADI VASISHT MANTRA
分类号 H03K3/12;H03K3/289 主分类号 H03K3/12
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