发明名称 PACKAGING METHOD FOR SEMICONDUCTOR DEVICE FOR CORRESPONDING TO CHIP SHRINK
摘要 A method for assembling a semiconductor package capable of coping with reduction of a chip size by packaging a semiconductor chip of a WBGA(wire bonding ball grid array) or FBGA(fine pitch ball grid array) type without varying the position and number of solder ball lands even if the semiconductor chip is reduced in size. A slit(115) for wire bonding is formed in the center of a substrate(102) having a plurality of columns of solder ball lands wherein more than two columns of solder ball lands(113) are not formed vertically with respect to the slit. Whether a semiconductor chip(104A,104B,104C) mounted on the substrate is wire-bonded through the slit is determined. If the wire bonding can be performed through the slit, the semiconductor chip is assembled as a face-down type to fabricate a WBGA. If not, the semiconductor chip is assembled as a face-up type to fabricate an FBGA. The semiconductor chip is a semiconductor chip which performs a memory function.
申请公布号 KR20060112303(A) 申请公布日期 2006.10.31
申请号 KR20050034019 申请日期 2005.04.25
申请人 SAMSUNG ELECTRONICS CO., LTD. 发明人 CHOI, JUNG HWAN
分类号 H01L21/56 主分类号 H01L21/56
代理机构 代理人
主权项
地址