发明名称 Interface bus protocol for managing transactions in a system of distributed microprocessor interfaces toward marco-cell based designs implemented as ASIC or FPGA bread boarding
摘要 A distributed interface between a microprocessor or a standard bus and user macro-cells belonging to an ASIC, FPGA, or similar silicon devices includes a main module connected to the microprocessor bus on one side and to a COMMON-BUS inside the interface on which a cluster of peripheral modules is appended on the other side. Peripheral modules are also connected to the user macro-cells through multiple point-to-point buses to transfer signals in two directions. A set of hardware and firmware resources such as registers, counters, synchronizers, dual port memories (e.g. RAM, FIFO) either synchronous or asynchronous with respect to macro-cells clock is encompassed in each peripheral module. Subsets of the standard resources are diversely configured in each peripheral module in accordance with specific needs of the user macro-cells.
申请公布号 US7130942(B2) 申请公布日期 2006.10.31
申请号 US20050081913 申请日期 2005.03.17
申请人 ITALTEL S.P.A. 发明人 GEMELLI RICCARDO;PAVESI MARCO;DE BLASIO GIUSEPPE
分类号 G06F13/14;G06F1/24;G06F12/08;G06F13/38;G06F13/40;G06F13/42;G06F17/50 主分类号 G06F13/14
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