| 摘要 |
The pipeline analog-to-digital converter has a number of subsequent comparator stages ( 2 ) where the thresholds of the comparator stages are adjusted in accordance with the digital conversion results from previous stages ( 18, 28, 38 ) so as to implement a non-linear conversion scale. In particular, the pipeline analog-to-digital converter consists of a number of comparator stages ( 2 ), which operate in accordance with a common clock signal. The comparator stages are connected in series in such a way that a residue signal from a previous stage is used as input signal of a subsequent stage for comparison during the next clock period of the clock signal. At least some of said comparator stages have, according to the invention, a threshold generator ( 25, 35, 45 ) for adjusting the threshold value of the respective comparator ( 22, 32, 42 ) in accordance with comparison results of previous comparator stages ( 18, 28, 38 ).
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