| 摘要 |
A synchronous data transfer circuit (3-0) synchronizes parallel data (DQ [0] to DQ [N]) of different timings for transfer to a transfer target (e.g. processor). The synchronous data transfer circuit includes a plurality of first flip-flop circuits (42-0 to 42-N) in which the parallel data are set by a data strobe signal (DQS [N:0]), a plurality of delay circuits (44-0 to 44-N), and a plurality of second flip-flop circuits (46-0 to 46-N). By configuring the second flip-flop circuits to share generation of a delay amount, the second flip-flop circuits are utilized for data synchronization by the synchronous data transfer circuit. Thus, it becomes possible to configure the delay circuits (44-0 to 44-N) with a remarkably reduced amount of delay elements (90). A plurality of the synchronous data transfer circuits (3-0, 3-1, 3-2, 3-3) may be provided in a memory controller (3), which may in turn form part of a computer system. |
