| 摘要 |
The invention discloses a delay-locked loop circuit (200) with input means (210) for a signal that is to be delayed, the input means comprising means for splitting the input signal into a first and a second branch. The signal in the first branch is connected to a component (220) for delaying the signal, and the signal in the second branch is used as a non-delayed reference for the delay caused by the delay component in the first branch. The delay component (220) is a passive tunable delay line, and the circuit comprises tuning means (230) for the tunable delay line, the tuning means being affected by said reference signal, and the first branch comprises output means for outputting a delayed signal with a chosen phase delay. Suitably, the delay component (220) is continuously tunable, for example a tunable ferroelectric delay line.
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