发明名称 LOGIC MODULE
摘要 FIELD: computer engineering. ^ SUBSTANCE: logic module contains two majority elements, AND element and OR element, first and second inputs of which are connected respectively to first, second inputs of AND element, while second, first inputs and output of second majority element are connected respectively to output of first majority element, second adjustment input and output of logic module. Introduced additionally are additional element AND, element OR and third majority element, output and second, third inputs of which are connected to respectively to third input of second majority element and output of element OR, output of additional element AND, connected by its first, second inputs respectively to first, second inputs of additional element OR, output of which is connected to second input of first majority element, connected by third input to output of element AND, first and second inputs of which are connected respectively to first and second information inputs of logic module, connected by third, fourth information and first adjustment inputs respectively to first, second inputs of additional element OR and to combined first inputs of first, third majority elements. ^ EFFECT: expanded functional capabilities due to provision of realization of any one of four simple symmetric Boolean functions, depending on four arguments - input binary signals. ^ 1 dwg
申请公布号 RU2286594(C1) 申请公布日期 2006.10.27
申请号 RU20050121619 申请日期 2005.07.08
申请人 GOSUDARSTVENNOE OBRAZOVATEL'NOE UCHREZHDENIE VYSSHEGO PROFESSIONAL'NOGO OBRAZOVANIJA "UL'JANOVSKIJ GOSUDARSTVENNYJ TEKHNICHESKIJ UNIVERSITET" 发明人 ANDREEV DMITRIJ VASIL'EVICH;ANDREEVA LJUDMILA SERGEEVNA
分类号 G06F7/57 主分类号 G06F7/57
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