| 摘要 |
A method for forming a gate pattern in a flash memory device is provided to avoid etch loading effect occurring in an etch process for forming a gate pattern without increasing the size between source select transistors by forming a hard mask etch assist pattern between photoresist patterns for defining a source select transistor. Patterns for defining a gate is formed on a semiconductor substrate having a conductive layer for a floating gate, a dielectric layer and a conductive layer for a control gate, including a photoresist pattern(SSLp) for defining a source select transistor. An etch assist pattern(A) is formed in a region adjacent to the pattern for defining the source select transistor. An etch process is performed using the gate defining pattern and the etch assist pattern as an etch mask to form a gate pattern. The gate defining pattern is composed of a pattern for defining the source select transistor, a pattern(W0p,W1p,W2p,W3p,W4p) for defining a cell transistor and a pattern for defining drain select transistor.
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