| 摘要 |
<p><P>PROBLEM TO BE SOLVED: To provide a processor controller capable of performing polling processing for a plurality of modules while suppressing a load on a processor. <P>SOLUTION: Polling processors 11c, 12c respectively output polling signals PS1, PS2 for stopping supply of signals to a processor core 1 upon access request from the processor core 1 when respective modules M1, M2 are performing respective processing. A polling selector 5 outputs to a clock control circuit 6 a WAIT signal WA for suspending a clock signal CL to be outputted to the processor core 1 based on designation by a single wait status register 11b or a multi-wait status register 11a. The clock control circuit 6 suspends the clock signal CL to be provided to the processor core 1 based on the WAIT signal outputted from the polling selector 5. <P>COPYRIGHT: (C)2007,JPO&INPIT</p> |
