发明名称 Semiconductor apparatus
摘要 Disclosed is a semiconductor apparatus adapted to reduce the inflow of current from an external input terminal in a power saving mode. A mode decision circuit 11 outputs to an interruption circuit 10 and a floating prohibiting circuit 15 a mode signal indicating whether operation of the semiconductor apparatus is power saving mode or regular operating mode. When the mode signal indicates the power saving mode, the interruption circuit 10 is rendered non-conductive to disconnect an external input terminal 13 on one hand and an input capacitance adjustment capacitor 12 and an initial stage input circuit 14 on the other hand from each other. The floating prohibiting circuit 15 also sets the voltage at an input end of the initial stage input circuit 14 at a preset voltage level. When the mode signal indicates the regular operating mode, the interruption circuit 10 is rendered conductive, such that the input capacitance adjustment capacitor 12 and the initial stage input circuit 14 are connected via a static charge breakdown prohibiting resistor device 21 to the external input terminal 13 to transmit an input signal of the external input terminal 13 to the initial stage input circuit 14.
申请公布号 US2006238236(A1) 申请公布日期 2006.10.26
申请号 US20060339799 申请日期 2006.01.26
申请人 ELPIDA MEMORY, INC. 发明人 TERAYAMA KAZUYOSHI
分类号 G05F1/10 主分类号 G05F1/10
代理机构 代理人
主权项
地址