发明名称 Processor, compiler and compilation method
摘要 In order to overcome the problem that conditionally executed instructions are executed as no-operation instructions if their condition is not fulfilled, leading to poor utilization efficiency of the hardware and lowering the effective performance, the processor decodes a number of instructions that is greater than the number of provided computing units and judges their execution conditions with an instruction issue control portion before the execution stage, Instructions for which the condition is false are invalidated, and subsequent valid instructions are assigned so that the computing units (hardware) is used efficiently. A compiler performs scheduling such that the number of instructions whose execution condition is true does not exceed the upper limit of the degree of parallelism of the hardware. The number of instructions arranged in parallel at each cycle may exceed the degree of parallelism of the hardware.
申请公布号 US2006242387(A1) 申请公布日期 2006.10.26
申请号 US20060452282 申请日期 2006.06.14
申请人 MATSUHITA ELECTRIC INDUSTRIAL CO., LTD. 发明人 HEISHI TAKETO;TAKAYAMA SHUICHI;TANAKA TETSUYA;OGAWA HAJIME;HIGAKI NOBUO
分类号 G06F9/44;G06F9/30;G06F9/318;G06F9/38;G06F9/45 主分类号 G06F9/44
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