NONVOLATILE SEMICONDUCTOR STORAGE DEVICE

摘要

In a flash memory (1), four banks (memory banks) (2a-2d) are formed clockwise from a right upper part of a semiconductor chip (CH). On lower parts of the banks (2a, 2b) and upper parts of the banks (2c, 2d), sense latches (4<SUB>1</SUB>-4<SUB>4</SUB>) are formed in a longitudinal direction of the semiconductor chip (CH), respectively. On lower parts of the sense latches (4<SUB>1</SUB>, 4<SUB>2</SUB>) and upper parts of sense latches (4<SUB>3</SUB>, 4<SUB>4</SUB>), main amplifier/data latch/selectors (5<SUB>1</SUB>-5<SUB>4</SUB>) are formed, respectively. An indirect peripheral circuit (6) is formed in the longitudinal direction of the semiconductor chip (CH) to be sandwiched by the main amplifier/data latch/selectors (5<SUB>1</SUB>-5<SUB>4</SUB>). A length of wiring which connects an input/output system control section (6d) and the main amplifier/data latch/selectors (5<SUB>1</SUB>-5<SUB>4</SUB>) is suppressed to be minimum by arranging the main amplifier/data latch/selectors (5<SUB>1</SUB>-5<SUB>4</SUB>) in the longitudinal direction of the semiconductor chip (CH) between the sense latches (4<SUB>1</SUB>-4<SUB>4</SUB>) and the indirect peripheral circuit (6).