| 摘要 |
<P>PROBLEM TO BE SOLVED: To enable even a low-speed tester to test a circuit operation at the time of restricted operation. <P>SOLUTION: In a semiconductor device provided with a clock synchronizing circuit and a plurality of replica delay circuit, and having a clock signal using them, a clock delay means is provided at a path of an internal clock so that timing relation of clock signals themselves becomes equal to timing relation in a synchronizing range even in out of range of synchronism of a clock synchronizing circuit. In the clock synchronizing circuit, there are a circuit for generating a clock (ACLK) for address/command and a circuit for generating a clock (QCLK) for data output. <P>COPYRIGHT: (C)2007,JPO&INPIT |
