发明名称 CLOCK GENERATING CIRCUIT
摘要 <P>PROBLEM TO BE SOLVED: To provide the frequency diffusion of an output clock signal so as to satisfy a fluctuation period fixed in a standard, etc., and the fluctuation range of a frequency without increasing a circuit scale and power consumption. <P>SOLUTION: A clock generating circuit includes an electric current route 160 for leaking an oscillation frequency control signal to control the oscillation frequency of a voltage control oscillator 110. The on/off-state of the output of a phase detector 120 is changed over by a prescribed period which corresponds to the counting result of a counter 170 for counting the number of cycles of the voltage control oscillator 110. When the output of the phase detector 120 is turned off, the oscillation frequency control signal is leaked in the electric current route 160 so as to reduce the oscillation frequency of the voltage control oscillator 110. When the output of the phase detector 120 is turned on, the oscillation frequency of the voltage control oscillator 110 which is reduced by feedback control is raised to the prescribed frequency. <P>COPYRIGHT: (C)2007,JPO&INPIT
申请公布号 JP2006295602(A) 申请公布日期 2006.10.26
申请号 JP20050114444 申请日期 2005.04.12
申请人 MATSUSHITA ELECTRIC IND CO LTD 发明人 ARIMA YUKIO
分类号 H03L7/08 主分类号 H03L7/08
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