| 摘要 |
PROBLEM TO BE SOLVED: To accurately control the DAM transfer of a plurality of data on a memory by a simple hardware configuration. SOLUTION: A descriptor table T0 corresponding to a queue Q0 and a descriptor table T1 corresponding to a queue Q1 are set on the memory 33. Numbers of descriptors forming the descriptor table T0 and numbers of descriptors forming the descriptor table T1 are recorded in registers R0 and R1 of a descriptor control part 51, respectively. The descriptors of the descriptor table T0 and the descriptors of the descriptor table T1 are recorded in caches C0 and C1 of a descriptor acquisition part 52, respectively. A descriptor selection part 53 selects either of the caches C0 and C1 according to a predetermined rule. The invention is applicable to every electronic device performing DMA transfer. COPYRIGHT: (C)2007,JPO&INPIT
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