| 摘要 |
<p>An information processing device and method for accurately controlling DMA transfer of data present in a memory with a simple hardware configuration. A memory (33) is provided with a descriptor table (T0) corresponding to a queue (Q0) and a descriptor table (T1) corresponding to a queue (Q1). In resistors (R0, R1) of a descriptor control section (51), the number of the descriptor constituting the descriptor table (T0) and the number of the descriptor constituting the descriptor table (T1) are recorded, respectively. In caches (C0, C1) of a descriptor acquiring section (52), the descriptors of the descriptor tables (T0, T1) are recorded, respectively. A descriptor selecting section (53) selects one of the caches (C0, C1) according to a predetermined rule. The invention can be applied to all the electronic devices which perform DMA transfer.</p> |
