发明名称 Semiconductor memory device
摘要 To reduce the area relating to location of redundant elements for relieving defects of a memory. A memory device has row address and input/output data as two dimensional redundancy parameters for relieving defects of an embedded memory 30 . It comprises a built-in self-test circuit 10 for testing defects of the embedded memory 30 , a redundant element location operator 20 for determining which redundant element replaces a defect based on a preset order and according to the order in which defects are detected by the self-test circuit 10 , and a row redundancy unit 31 and an I/O redundancy unit 32 for replacing the defects in the embedded memory according to the determined order. The redundant element location operator 20 determines the priority axis according to the preset order and according to the order in which the defects are detected, and holds redundant element location information.
申请公布号 US2006239090(A1) 申请公布日期 2006.10.26
申请号 US20060408995 申请日期 2006.04.24
申请人 NEC ELECTRONICS CORPORATION 发明人 ANAZAWA KAZUHITO;KITAZAWA EIJI
分类号 G11C29/00 主分类号 G11C29/00
代理机构 代理人
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