发明名称 LOGICAL GATE AND LOGIC CIRCUIT
摘要 PROBLEM TO BE SOLVED: To provide a logical gate in which a sub threshold leakage current is reduced. SOLUTION: The logical gate has a first transistor in which a first voltage is applied to a source and a first input signal is inputted to a gate and which outputs a first output signal from a drain, a second transistor in which a second voltage lower than the first voltage is applied to a source and a second input signal is inputted to a gate and which outputs a second output signal from a drain, and a connection switching part connected between the drains of the first/second transistors and connecting or disconnecting first/second transistors. COPYRIGHT: (C)2007,JPO&INPIT
申请公布号 JP2006295439(A) 申请公布日期 2006.10.26
申请号 JP20050111853 申请日期 2005.04.08
申请人 ELPIDA MEMORY INC 发明人 NAGATA KYOICHI
分类号 H03K17/687;H03K17/30;H03K19/0948;H03K19/20 主分类号 H03K17/687
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