发明名称 SEMICONDUCTOR DEVICE AND ITS MANUFACTURING METHOD
摘要 PROBLEM TO BE SOLVED: To provide a semiconductor device and its manufacturing method capable of improving reliability deterioration due to bad via conduction based on bad via embedding without causing increases of inter-wiring capacitance and an RC delay amount. SOLUTION: A lower layer wiring 3 is embedded at a predetermined position on a first interlayer insulating film 1 by SiO<SB>2</SB>or the like, and the lower layer wiring 3 is coated with a barrier metal 2. An organic film 5 made of PAE whose chief component is C is provided on an upper surface of a lower layer wiring 3 and a wafer 1, and a second interlayer insulating film 6 made of SiO<SB>2</SB>, SiOC, SiC, and SiCN or the like is formed over the entire surface of the organic film 5, and further an upper layer wiring 8 and a via 9 are provided on the second interlayer insulating film 6. COPYRIGHT: (C)2007,JPO&INPIT
申请公布号 JP2006294941(A) 申请公布日期 2006.10.26
申请号 JP20050115107 申请日期 2005.04.12
申请人 TOSHIBA CORP 发明人 NAKAMURA NAOFUMI
分类号 H01L21/768;H01L21/312;H01L23/522 主分类号 H01L21/768
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