发明名称 MULTILEVEL INTERCONNECTION, ITS MANUFACTURING METHOD, FLAT PANEL DISPLAY AND ITS MANUFACTURING METHOD
摘要 PROBLEM TO BE SOLVED: To manufacture a lower-cost multilevel interconnection which is connected with a via hole finer than a conventional one while a gap is difficult to remain in the via hole. SOLUTION: There is an inter-layer insulating film 18 on a first metal wiring 11. A second metal wiring 19 is formed on the inter-layer insulating film 18. The first metal wiring 11 and the second metal wiring 19 are connected together through the via hole. A manufacturing method comprises a step for forming a via post 13 on the first metal wiring 11; a step for printing an inter-layer insulating film 18 lower than the height of the via post 13, by using a screen plate 17 having a non-ejection area 16 slightly larger than a head of the via post 13, while generally aligning the non-ejection area 16 with the head of the via post 13; a step for curing the inter-layer insulating film 18; and a step for forming the second metal wiring 19, connected to the via post 13, on the inter-layer insulating film 18. COPYRIGHT: (C)2007,JPO&INPIT
申请公布号 JP2006295116(A) 申请公布日期 2006.10.26
申请号 JP20050306592 申请日期 2005.10.21
申请人 RICOH CO LTD 发明人 MURAKAMI AKISHIGE;KAWASHIMA IKUE;AKIYAMA ZENICHI
分类号 H05K3/46;G02F1/167 主分类号 H05K3/46
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