| 摘要 |
A dynamic shift register includes a first stage ( 21 ) and a second stage ( 22 ). The first stage includes a logical inputting port ( 201 ), a first retaining circuit ( 231 ), and a first transmitting gate ( 211 ). The first transmitting gate includes an input connected to the logical inputting port, and an output connected to the first retaining circuit. The second stage includes a logical outputting port ( 205 ), a second retaining circuit ( 232 ), and a second transmitting gate ( 212 ). The second transmitting gate includes an input connected to the output of the first transmitting gate, and an output connected to the logical outputting port and the second retaining circuit. In a cycle, after the clock signal and the complementary clock signal are stopped, the dynamic shift register can stably retain the logical signal.
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