发明名称 EFFICIENT VIDEO DECODING ACCELERATOR
摘要 <p>The present invention relates to a decoding apparatus and method for decoding compressed video data having a plurality of video frames with a plurality of blocks, wherein the video frames are split in a first predetermined direction into at least two stripes whose width does not exceed a hardware prediction line size. Then, coefficient prediction is performed on one of the at least two stripes to provide a predictor in a second predetermined direction for at least one other of the at least two stripes, the second predetermined direction being perpendicular to the first predetermined direction. Additionally, fake blocks are generated to be inserted into the at least one other of said at least two stripes in order to initialize prediction in the second predetermined direction. Thereby, hardware accelerators with fixed processing width can be used in a more flexible manner.</p>
申请公布号 WO2006111915(A1) 申请公布日期 2006.10.26
申请号 WO2006IB51175 申请日期 2006.04.14
申请人 KONINKLIJKE PHILIPS ELECTRONICS N.V.;PLAGNE, GERAUD 发明人 PLAGNE, GERAUD
分类号 H04N7/26;H04N7/30 主分类号 H04N7/26
代理机构 代理人
主权项
地址