Self correcting suppression of threshold voltage variation in fully depleted transistors

摘要

A semiconductor fabrication method includes implanting or otherwise introducing a counter doping impurity distribution into a semiconductor top layer of a silicon-on-insulator (SOI) wafer. The top layer has a variable thickness including a first thickness at a first region and a second thickness, greater than the first, at a second region. The impurity distribution is introduced into the top layer such that the net charge deposited in the semiconductor top layer varies linearly with the thickness variation. The counter doping causes the total net charge in the first region to be approximately equal to the net charge in the second region. This variation in deposited net charge leads to a uniform threshold voltage for fully depleted transistors. Fully depleted transistors are then formed in the top layer.