发明名称 System and method for dynamic rank specific timing adjustments for double data rate (DDR) components
摘要 In some embodiments, a system and method for making rank-specific adjustments to the READ tenure parameters of a double data-rate (DDR) memory component to improve the DDR bus timing margins. When a READ tenure is encountered for the DDR memory component, the rank of the DDR memory component is calculated and the value is used to retrieve two adjustment signals, which are specific to the DDR memory component, from the look up table. One of the adjustment signals is used to adjust a gating signal for the data strobe signal of the component. The other adjustment signal is used to fine tune a required ¼ clock delay for the data strobe signal to read the data from the DDR memory component while adjusting for the inherent latency of the DDR memory component. Other embodiments are described and claimed.
申请公布号 US7127584(B1) 申请公布日期 2006.10.24
申请号 US20030713718 申请日期 2003.11.14
申请人 INTEL CORPORATION 发明人 THOMPSON DEREK A.;MCGINNIS DARRELL S.;ZUMKEHR JOHN F.
分类号 G06F12/00 主分类号 G06F12/00
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