发明名称 |
Segmented addressable scan architecture and method for implementing scan-based testing of integrated circuits |
摘要 |
The present invention provides a segmented addressable scan architecture and method for implementing scan-based testing of integrated circuits. A scan chain is divided into a plurality of segments. For a test pattern, compatible segments of the plurality of segments are grouped into compatibility classes. All compatible segments or a subset of them within one of the compatibility classes are simultaneously loaded through selective activation.
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申请公布号 |
US2006236176(A1) |
申请公布日期 |
2006.10.19 |
申请号 |
US20050097936 |
申请日期 |
2005.03.31 |
申请人 |
ALYAMANI AHMAD A;GRINCHUK MIKHAIL I;CHMELAR ERIK |
发明人 |
ALYAMANI AHMAD A.;GRINCHUK MIKHAIL I.;CHMELAR ERIK |
分类号 |
G01R31/28 |
主分类号 |
G01R31/28 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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