摘要 |
<p>A multiplexer circuit in a memory organized into page-portions (210, 250) has a plurality of bit- select multiplexers (216, 256) configured to couple a plurality of page-portion global bitlines (214, 254) to a sense amplifier (201) input. A plurality of column address lines organized into data bytes comprises each page-portion. A plurality of column multiplexers (212, 252) couple the data bytes to the page-portion global bitlines (214, 254) such that each of the address lines comprising the data byte is coupled to one of the page-portion global bitlines (214, 254).</p> |
申请人 |
ATMEL CORPORATION;SON, JINSHU;WANG, LIQI;LE, MINH, V.;NG, PHILIP, S. |
发明人 |
SON, JINSHU;WANG, LIQI;LE, MINH, V.;NG, PHILIP, S. |