| 摘要 |
The present invention provides a shift register which can operate favorably without providing a level shift portion. The first clocked inverter at the (2n-1)-th stage operates in accordance with the first output from the previous stage, an output from the second clocked inverter at the previous stage, and the first CK signal; the second clocked inverter at the (2n-1)-th stage operates in accordance with the second output from the previous stage, an output of the first clocked inverter at the (2n-1)-th stage, and the first CK signal; one of the first output and the second output is equal to a potential of VDD and the other is equal to a potential of VSS; the first CK signal at the 2n-th stage operates the third output from the (2n-1)-th stage, an output of the second clocked inverter and the second CK signal; the second clocked inverter at the 2n-th stage operates in accordance with the fourth output from the (2n-1)-th stage, an output from the first clocked inverter at the 2n-th stage, and the second CK signal; one of the third output and the fourth output is equal to the potential of VDD and the other is equal to the potential of VSS, and the second CK signal is an inversion signal of the first CK signal and the amplitude of the CK signal is smaller than the power supply potential.
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