| 摘要 |
PROBLEM TO BE SOLVED: To reduce the current consumption of a cache memory without deteriorating a function in an integrated circuit device having a CPU with built-in cache memory. SOLUTION: This integrated circuit device 10 comprises a CPU 20, a cache memory 30, a cache interface circuit 40, and a cache data bus having a bus width larger than the request data width of the CPU. The cache interface circuit 40 reads data for the bus width of the cache data bus larger than the request data width of the CPU based on a request address, holds the read data in the request data width units of the CPU so as to be freely fetched, outputs the data held in a data holding circuit toward the CPU when data of the request address from the CPU are held in the data holding circuit, and generates and outputs, in a cycle where no access to the cache memory according to the request address from the CPU is performed, a low-power control signal for stopping the clock of the cache memory or reducing the power thereof. COPYRIGHT: (C)2007,JPO&INPIT
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