发明名称 LAYOUT DESIGN METHOD, LAYOUT DESIGN PROGRAM AND LAYOUT DESIGN DEVICE
摘要 PROBLEM TO BE SOLVED: To provide a layout design method, a layout design program and a layout design device capable of performing layout design in a short time while suppressing a bad effect of cross-talk or the like by performing rough wiring after estimating the load of wiring. SOLUTION: Signal lines in which signals are transferred in the same time unit are classified to a simultaneous transition group based on cell arrangement information, signal lines belonging to the simultaneous transition group are assigned to Gcells at double or more wiring track pitches, and first delay information is assigned to the assigned signal lines for each Gcell to perform a timing analysis. The time unit for transferring the signals is reevaluated to update the simultaneous transition group, and whether signal lines belonging to the updated simultaneous transition group can be arranged at the double or more wiring track pitches or not. When they cannot be arranged at the double or more pitches, the signal lines are reassigned to the Gcells, and the processing is performed again. COPYRIGHT: (C)2007,JPO&INPIT
申请公布号 JP2006285445(A) 申请公布日期 2006.10.19
申请号 JP20050102362 申请日期 2005.03.31
申请人 FUJITSU LTD 发明人 HORI TOSHIKAZU;YABUTA TAKUSHI;FUKUSHIMA HIROYUKI
分类号 G06F17/50;H01L21/82 主分类号 G06F17/50
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