| 摘要 |
<p><P>PROBLEM TO BE SOLVED: To reduce the overall chip size by including a page buffer and reducing a coupling capacitance component between sensing nodes. <P>SOLUTION: The page buffer circuit of a flash memory device includes a plurality of page buffers connected to a predetermined number of bit lines, respectively, and also connected to a Y-gate circuit, and the page buffers performs a read operation or program operation at the same time in response to bit line control signals, bit line select signals, and control signals. Each of the plurality of page buffers stores sensing data corresponding to read-out data received from any one line of the bit lines set in the read operation, outputs the stored sensing data to the Y-gate circuit, stores program data received from the Y-gate circuit at the time of program operation, and outputs the stored program data to any one line of the predetermined number of bit lines. <P>COPYRIGHT: (C)2007,JPO&INPIT</p> |
