发明名称 HIGH-SPEED SAMPLING ARCHITECTURE
摘要 A high-speed sampling system (Fig. 6) and an analog to digital converter (620, 622, 624) are disclosed. One embodiment of a method of sampling (610, 620, 622, 624) a signal includes receiving an analog signal and generating first samples at a rate of Fs, and generating second sub-samples (M bit @Fs/n) from the first samples at a rate of Fs/N and having a relative phase of approximately (360/N)*(i-1) degrees, where i varies from 1 to N. In a first embodiment, at most two second sub- samplers are tracking the output of the first sampler at any point in time. In a second embodiment, only one of the N second sub-samplers are tracking the output of the first sampler at any point in time. A third embodiment further includes generating third samples from the second samples at a rate of Fs/N, and having a relative phase of approximately ((360/N)*(i-1)+180) degrees. A method of interleaved analog to digital converting includes corresponding time interleaved ADCs receiving the third samples.
申请公布号 WO2006076420(A3) 申请公布日期 2006.10.19
申请号 WO2006US00959 申请日期 2006.01.12
申请人 发明人 GUPTA, SANDEEP, KUMAR;ZABRODA, OLESTY
分类号 H03M1/00 主分类号 H03M1/00
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