| 摘要 |
<p><P>PROBLEM TO BE SOLVED: To provide a page buffer circuit of a flash memory device in which stable precharge voltage is supplied to bit lines and read-out of erroneous data can be prevented without being affected by variation of temperature and voltage in the read operation. <P>SOLUTION: The page buffer circuit of a flash memory device includes page buffers PB1 to PB2K connected to the plurality of bit line pairs BLe1..., BLo1..., respectively, and performing simultaneously read operation or program operation on the memory cells in response to bit line control signals, bit line select signals and control signals. Also the circuit includes bit line precharge circuits connected to the plurality of bit line pairs, respectively, and in the read operation, simultaneously precharging one of a pair of bit lines connected thereto to reference voltage level in response to the bit line precharge signal. <P>COPYRIGHT: (C)2007,JPO&INPIT</p> |
