发明名称 LAYOUT VERIFICATION METHOD, LAYOUT VERIFYING DEVICE, AND LAYOUT DESIGN DEVICE
摘要 PROBLEM TO BE SOLVED: To enable it to verify a layout rule corresponding to working voltage only by using an actual process. SOLUTION: Two or more layers are provided with circuit constituents for integrated circuits where two or more working voltages are used, and among the two or more layers, a specific layer is dissociated is arranged with high voltage circuit constituents so that each layer may recognize its working voltage so as to verify the layout by applying the working voltage according the working voltage. It is made possible to perform the layout verification by the layout rules according to the working voltage, without generating newly a dummy layer etc. , only by using a layer used on an actual process, and by recognizing the circuit constituents applied with which a high voltage on a layout. COPYRIGHT: (C)2007,JPO&INPIT
申请公布号 JP2006286792(A) 申请公布日期 2006.10.19
申请号 JP20050102718 申请日期 2005.03.31
申请人 FUJITSU LTD 发明人 DEURA MANABU
分类号 H01L21/82;G06F17/50 主分类号 H01L21/82
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