| 摘要 |
A duty detection circuit is provided with a main circuit unit that includes at least a first capacitor that is discharged during the time period in which the clock signal is at a high level and charged during the time period in which the clock signal is at a low level, and a second capacitor that is charged during the time period in which the clock signal is at a high level and discharged during the time period in which the clock signal is at a low level, with the main circuit unit alternately charging or discharging the first and second capacitors in synchrony with the clock signal; and a duty correction signal generator for detecting the potential difference of the first and second capacitors and outputting a duty correction signal based on the potential difference.
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